肖特基二极管
光电子学
二极管
材料科学
肖特基势垒
MOSFET
静电放电
电气工程
高压
电压
CMOS芯片
晶体管
工程类
作者
Po-Lin Lin,Shen-Li Chen,Sheng-Kai Fan
出处
期刊:IEEE Electron Device Letters
[Institute of Electrical and Electronics Engineers]
日期:2020-09-09
卷期号:41 (11): 1673-1676
被引量:1
标识
DOI:10.1109/led.2020.3023021
摘要
This study with the area-efficient design for improving electrostatic discharge (ESD) and Latch-up (LU) abilities in the ultra-high voltage (UHV) n-channel Lateral-Diffused MOSFET (nLDMOS) is investigated via a TSMC 0.5-μm UHV Bipolar CMOS DMOS (BCD) process. There are two architectures of these nLDMOS devices with embedded Schottky diodes in the electrode area. Firstly, the drain side is divided into three concentric circles and embedded with Schottky diodes. The influence of these samples with different layout arrangements on ESD is evaluated. For the second item, UHV nLDMOS devices with the source side embedded Schottky diodes by two alternative layout types are developed. Experimental results showed that an UHV nLDMOS with embedded Schottky diodes at the drain side can significantly improve ESD ability, especially for the fully embedded Schottky diodes at the drain side (being with the highest figure of merit (FOM) value in the ESD, LU, and cell-area considerations). On the other hand, with embedded Schottky diodes at the source side can increase the holding voltage which can effectively improve the LU immunity.
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