Strain Engineering in Si Split-Gate Trench Power MOSFETs by Partial Oxidation of Polysilicon Electrodes

材料科学 应变工程 电极 拉伤 MOSFET 电气工程 光电子学 拓扑(电路) 物理 电压 量子力学 工程类 晶体管 医学 内科学
作者
Stefan Karner,M. Rösch,Germano Galasso,Seung Hwan Lee,Oliver Blank
出处
期刊:IEEE Transactions on Electron Devices [Institute of Electrical and Electronics Engineers]
卷期号:70 (3): 1168-1175 被引量:4
标识
DOI:10.1109/ted.2022.3230917
摘要

Performance improvement of Si split-gate trench power MOSFETs due to conventional scaling is approaching a physical and economical limit. Strain engineering, however, enables enhanced device characteristics without the need for further shrinkage as a result of an increased charge carrier mobility in monocrystalline Si. In this work, thermally grown SiO $_{\mathbf {2}}$ functional strain layers are introduced into a state-of-the-art Si trench power MOSFET by partial oxidation of the source and gate electrode. The influence of the additional SiO2 layers on the strain distribution in monocrystalline Si is described by the thermomechanical (TM) strain simulation and the resulting device properties are assessed by means of detailed electrical analysis. For the strain-modified devices, the simulation shows higher longitudinal tensile strains in the direction of current flow and stronger out-of-plane compressive strains perpendicular to it, which have a beneficial effect on the electron mobility. The electrical characterization revealed improved ON-state resistances at gate voltages of 4.5 V ( ${R}_{ON}4.5$ ) and 10 V ( ${R}_{ON}10$ ) of up to 16.8% and 13.8%, respectively, while the breakdown voltage did not change. In the presence of the SiO2 layer in the gate electrode, the threshold voltage was reduced, which also contributed to the ${R}_{ON}$ improvement. The functional strain layer in the gate electrode mainly influences the mobility in the channel, while it primarily alters the mobility in the drift region when introduced into the source electrode. However, the modification of mechanical strain in the channel area shows less impact on the overall device performance compared to the drift region.
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