Simulation Study on SEB Resistance of Silicon-based RESURF LDMOS Device with Drain Buffer Layer

The power LDMOS device is vulnerable to the influence of high-energy particles in the space radiation environment, which leads to the single event burn-out, makes the device fail and destroys the electronic system of the spacecraft, which will seriously threaten its full operation in orbit. It is necessary to reinforce the design of the device to improve the resistance to single event burn-out[3]. Therefore, this paper proposes a new 650V Si-based power RESURF LDMOS device-RESURF LDMOS with Buffer Layer and P, N Buried (NPBNB-MOS), and introduces and analyzes the device structure and working principle of NPBNB-MOS. Simulation based on Sentaurus TCAD tool. NPBNB-MOS, RESURF LDMOS with Buffer Layer and P Buried (PBNB-MOS), RESURF LDMOS with P Buried (PB-MOS) and Conventional RESURF LDMOS (C-MOS) are simulated. The basic electrical characteristic curves and SEB characteristic curves of the four devices are obtained, and the simulation results of the four devices are compared and analyzed. The results show that under the same incident position, LET value and particle ionization radius, the SEB threshold voltage of NPBNB-MOS device proposed in this paper is higher, which is 116 % higher than that of C-MOS device, 47 % higher than that of PB-MOS device, and 14 % higher than that of PBNB-MOS device.