A Design of Low-Power Dynamic Latch Comparator with Adaptive Power Control for12-bit Charge Sharing SAR ADCs

This paper presents a dynamic latch comparator implemented with Adaptive Power Control (APC) composed of a 12-bit charge-sharing Analog-toDigital Converter (ADC), targeting a low area and low power in integrated RF transmission for ultrasound diagnostic medical devices. The proposed ADC comprises of switches and unit array capacitors with low threshold voltage devices, thereby minimizing the ADC size. The APC structure lowers the consumption of power. The dynamic performance of proposed ADC with a dynamic latch having APC has an Effective Number of Bits (ENOB) of 11.34-bits and Signal and Signal to Noise Distortion Ratio (SNDR) of 70.03 dB at 5 MHz input frequency. The designed ADC is implemented with 0.13 urn CMOS process occupying an area of 1600 μm x 505 μm. The designed SAR ADC draws 1.42 mA current per channel at a sampling rate of 20 MSPS.