Design of A Reference Buffer with Ultralow Output Resistance for High-speed ADCs

This paper presents the design of an ultralow-outputresistance reference voltage buffer (RVB) that provides differential reference voltages (VREFP and VREFN) for high-speed high-resolution successive-approximationregister analog-to-digital converters (SAR ADCs). The proposed RVB innovatively combined the advantages of both the flipped voltage follower (FVF) and the super source follower (SSF) by parallel arrangement and sharing current, lowering the output resistance and power consumption simultaneously. In order for the RVB to be more adaptive in terms of reference voltage error (corrected by gain error calibration algorithm), the reference voltage is readily adjustable via the parallel CMOS current source flowing from the upper to the lower part of the RVB. Implemented in 40nm CMOS technology, the proposed RVB achieved an output resistance of 6.2~19.6Ohm with a current of only 2~13mA, which is the lowest among other architectures both theoretically and practically.