覆盖
计量学
计算机科学
抵抗
平版印刷术
极紫外光刻
失真(音乐)
节点(物理)
半导体器件制造
薄脆饼
可靠性工程
光学
材料科学
计算机网络
纳米技术
工程类
物理
放大器
结构工程
带宽(计算)
图层(电子)
程序设计语言
作者
Takahiro Matsumoto,Hideki Ina,Koichi Sentoku,Satoru Oishi
摘要
With the advancement of lithography, the overlay budget is becoming extremely tight. As the accuracy of overlay is important for achieving a good yield, the demand for the accuracy of overlay is ever increasing. According to the International Technology Roadmap for Semiconductors (ITRS), the overlay control budget for the 32nm technology node will be 5.7nm. The overlay metrology budget is typically 1/10 of the overlay control budget resulting in overlay metrology total measurement uncertainty (TMU) requirements of 0.57nm for the most challenging use cases of the 32nm node. The current state of the art imaging overlay metrology technology does not meet this strict requirement, and further technology development is required to bring it to this level. Especially for exposure tool inspection (e.g. alignment, overlay, wafer stage and distortion), more high accuracy should be required using 'resist to resist' pattern. In this work we simulated the measurement sensitivity for two types of scatterometry based overlay metrology, one is differential signal scatterometry overlay (SCOL), the other is double exposure type (DET).
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