The Adiabatically Driven StrongARM Comparator

Adiabatic logic, also known as charge recovery logic, is subject to active research in the field of low-energy computation. Although the principles of adiabatic operation are well understood in digital circuits, analog and mixed-signal circuit implementations are largely unexplored. This brief shows that the strongARM comparator can take advantage of adiabatic principles by: 1) being powered by a sine-wave, the power-clock, rather than the conventional dc power supply, V _DD and 2) using an adiabatic buffer as the output stage, rather than an SR-latch. Post-layout simulations in a 65-nm technology show that the adiabatically driven strongARM has similar characteristics to the traditional strongARM: +2% noise, +0.1% input offset voltage, and the same regeneration time-constant, while only consuming between 28% and 55% of the energy of the traditional strongARM, in the typical case.