材料科学
多晶硅
薄膜晶体管
光电子学
排水诱导屏障降低
阈值电压
晶体管
电气工程
电压
硅
电场
泄漏(经济)
纳米技术
工程类
物理
图层(电子)
量子力学
经济
宏观经济学
作者
J. Park,Kyungsoo Jang,Dongjoo Shin,Myunhun Shin,J.S. Yi
标识
DOI:10.1016/j.sse.2018.07.009
摘要
Thin film transistors have become crucial components of several electronic display devices. However, high leakage current is a frustrating impediment to increasing the efficiency of these transistors. We have performed an experimental and quantitative study on the effects of off-state bias stress on the characteristics of a p-type polycrystalline silicon (poly-Si) thin film transistor (TFT). The gate-induced drain leakage (GIDL) current under off-state bias stress conditions was investigated by changing gate-source voltage (Vgs) and drain-source voltage (Vds). Off-state bias stress was found to dramatically increase the threshold Vgs from 1 to 11 V, thereby increasing the voltage needed to turn off the TFT, without causing significant changes in on-state current or subthreshold swing. We developed local defect creation and charge trapping models for a technology computer-aided design simulation platform to understand the mechanisms underlying these observed effects. Using the model, we showed that off-state stress induces charge trapping within the local defects of a high electric field region in the TFT channel near the drain. This reduces the electric field and thermionic field-emission current, which in turn lowers the GIDL current by increasing threshold voltage Vgs.
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