An RS (255,239) Decoder with e-PIBM Algorithm, 25.6Gb/s Throughput and 623 TSNT FoM Value Using Fractional Folding Technique in 40nm Technology

This paper proposes a novel Fractional Folding (FF) architecture for digital signal processing integrated circuits. With this new structure, a Fractional Folding based enhanced Parallel Inversionless Berlekamp-Massey (FF-ePIBM) Reed-Solomon Decoder is presented of which the number of processing element (PE) can be reduced to only one, resulting in ultra-low hardware complexity. The FF-ePIBM VLSI architecture can greatly reduce the hardware cost by about 60% compare to the fully expanded parallel ePIBM architecture. A polyphase clock signal is needed in order to achieve fractional folding function according to specific fractional-factor. It is generated from Delay Locked Loop (DLL) commonly embedded in almost all VLSI circuit and system. To maximize the throughput of decoder, pipelined architecture is adopted to optimize critical path delay. The RS (255, 239) decoder with FF-ePIBM architecture is finally implemented with 40nm CMOS technology. The synthesized results demonstrate that the decoder has a gate count of 12.6k and can operate at 3.2GHz to achieve a highest throughput of 25.6Gb/s and a best TSNT FoM value of 623 to this date.