超大规模集成
计算机科学
折叠(DSP实现)
CMOS芯片
吞吐量
关键路径法
门计数
并行计算
多相系统
时钟频率
解码方法
算法
计算机硬件
嵌入式系统
电子工程
电信
工程类
电气工程
系统工程
无线
作者
Wenwen Liu,Sheng Wang,Qinghao Lin,Lei Zhu,Jing-Wei Shi,Min Lin
标识
DOI:10.1109/iscas51556.2021.9401210
摘要
This paper proposes a novel Fractional Folding (FF) architecture for digital signal processing integrated circuits. With this new structure, a Fractional Folding based enhanced Parallel Inversionless Berlekamp-Massey (FF-ePIBM) Reed-Solomon Decoder is presented of which the number of processing element (PE) can be reduced to only one, resulting in ultra-low hardware complexity. The FF-ePIBM VLSI architecture can greatly reduce the hardware cost by about 60% compare to the fully expanded parallel ePIBM architecture. A polyphase clock signal is needed in order to achieve fractional folding function according to specific fractional-factor. It is generated from Delay Locked Loop (DLL) commonly embedded in almost all VLSI circuit and system. To maximize the throughput of decoder, pipelined architecture is adopted to optimize critical path delay. The RS (255, 239) decoder with FF-ePIBM architecture is finally implemented with 40nm CMOS technology. The synthesized results demonstrate that the decoder has a gate count of 12.6k and can operate at 3.2GHz to achieve a highest throughput of 25.6Gb/s and a best TSNT FoM value of 623 to this date.
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