CMOS芯片
电子工程
灵敏度(控制系统)
带宽(计算)
电气工程
物理
计算机科学
电信
工程类
作者
Hao Li,Chia‐Wei Hsu,J. Sharma,James Jaussi,Ganesh Balamurugan
出处
期刊:IEEE Journal of Solid-state Circuits
[Institute of Electrical and Electronics Engineers]
日期:2022-01-01
卷期号:57 (1): 44-53
被引量:22
标识
DOI:10.1109/jssc.2021.3110088
摘要
Optical receivers (ORXs) with integrated CMOS electronics enable compact, low-power solutions for 400-G Ethernet and co-packaged optics. In this article, we present a 100-Gb/s PAM-4 ORX with TIA and sampler integrated into a single 28-nm CMOS IC. ORX sensitivity is optimized using a low noise, sub-Nyquist bandwidth TIA followed by a mixed signal sampler that includes 2-tap FFE and 2-tap DFE. A distributed current-integrating summer helps meet feedback latency requirements of 50-Gbaud direct-feedback PAM-4 DFE. Measurements characterizing the CMOS linear TIA indicate ~23-GHz trans-impedance (ZT) bandwidth (BW) with- $2.5~\mu \text{A}_{\mathrm {rms}}$ input-referred noise. Optical measurement results at 100 Gb/s show that −8.9-dBm sensitivity is achieved at 2.4e-4 BER with 3.9-pJ/bit energy efficiency.
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