Low Area and High Throughput Architectures of FIR Filter for Data Streaming DSP Applications

Finite Impulse Response (FIR) Filter occupied a significant position in most of Digital Signal Processing (DSP) Applications. The behaviour of FIR filters can be realized in software for DSP applications and executed on Digital Signal Processor architectures. These kinds of digital filters consider digital components, digital input and perform mathematical computations to produce digital output. In modern DSP applications demanding area efficient architecture for DSP algorithms while optimizing throughput. This can be achieved by design of hardware architectures for DSP algorithms and apply design optimization techniques to accelerate the throughput and minimize area. This article attempts to develop hardware architectures for FIR Filter and apply the design optimization techniques present in literature. In this article, High Level Synthesis concepts were adapted to develop hardware architecture for FIR filter and optimization techniques have been applied to optimize design attributes like area, throughput and power. Finally, design attributes are summarized after applying optimization techniques and published significant architectural attributes suitable for real life DSP applications.