材料科学
退火(玻璃)
无定形固体
原子层沉积
光电子学
阈值电压
薄膜晶体管
晶体管
电压
薄膜
复合材料
纳米技术
图层(电子)
电气工程
结晶学
化学
工程类
作者
Dong-Gyu Kim,Won-Bum Lee,Seung Hee Lee,Jeongwook Koh,Bong Jin Kuh,Jin‐Seong Park
标识
DOI:10.1021/acsami.3c06517
摘要
Highly stable IGZO thin-film transistors derived from atomic layer deposition are crucial for the semiconductor industry. However, unavoidable defect generation during high-temperature annealing results in abnormal positive bias temperature stress (PBTS). Herein, we propose a defect engineering method by controlling the gate insulator (GI) deposition temperature. Applying a GI deposition temperature of 400 °C to the In0.52Ga0.18Zn0.30O active layer effectively suppresses defects even after 600 °C annealing, preserving the amorphous phase of IGZO. The device exhibits a threshold voltage (VTH) of 0.05 V, a field-effect mobility of 27.6 cm2/Vs, a subthreshold swing of 61 mV/decade, and a hysteresis voltage of 0.01 V, demonstrating highly reliable PBTS and negative bias temperature stress. A power-law fit of the PBTS stability under 2 MV/cm of gate field stress and 120 °C of temperature stress predicts a VTH shift of -0.01 V after 10 years. Moreover, the proposed method ensures reliable uniformity over a large 4 in. area.
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