Design of a Low-Jitter Digitally Controlled Oscillator With Supply Noise Compensation

This paper proposes a clock buffer with compensator technology to achieve low-jitter design in the digitally controlled oscillator (DCO). The compensator consists of a PMOS transistor and a MOS capacitor. The compensator that provides the opposite sensitivity to the delay cell is connected to the node between each delay cell. The compensated DCO has a reduced jitter of approximately 12.7-ps (peak-to-peak) based on the 3-GHz output frequency under ±0.1% VDD noise.