A Fully Integrated Low Voltage DRAM with Thermally Stable Gate-first High-k Metal Gate Process

A 35nm node 4Gbit LPDDR3 prototype with high-k metal gate (HKMG) peripheral transistors is implemented for the first time using processes that are fully compatible with those of conventional commercial DRAMs with poly/SiON (PSiON) transistors. This paper describes that the HKMG transistors in the peripheral circuits drastically reduce operating voltage from 1.2V to less than 0.95V. At the same time, both retention time and tRDL are improved due to >30% reduction of the threshold voltage (Vth) mismatch in sense amplifiers which is majorly induced by random dopant fluctuation (RDF) phenomenon. Lastly, chip size can be reduced as the increase of drivability allows the gate width of transistors to be scaled down.