A 1.2V 86dB SNDR 500kHz BW Linear-Exponential Multi-Bit Incremental ADC Using Positive Feedback in 65nm CMOS

This paper presents a linear-exponential two-phase multi-bit incremental ADC (IADC). The exponential integration in the proposed IADC is generated by positively feedback the integrator output to the input, which can accumulate the signals stably due to the reset operation in IADC. To avoid the nonlinearity due to the signal-dependent charge injected from the reference, this work separates the sampling capacitor and the DAC capacitor. It will relax the requirement of reference buffer for fast-settling under a high sample rate. Then, we reconfigure the DAC capacitor to directly offer the exponential integration, resulting in saving in the usage of integration capacitor with a compact implementation. The linear-exponential two-phase scheme provides data-weighted-averaging-friendly weighting function to suppress the multi-bit DAC mismatch error. Fabricated in a 65nm CMOS under 1.2 V supply and clocked at 128MHz, the ADC achieves an SNDR/DR/SFDR of 86.02/94.6/103.03dB with 500kHz BW, 20mW & 0.26mm ² , resulting in FoMs of 168.57dB.