A Logic-in-Memory Computer

计算机科学 内存映射 计算机存储器 并行计算 仅缓存内存体系结构 隐藏物 控制逻辑 交错存储器 计算机硬件 虚拟内存 半导体存储器 内存管理
作者
Harold S. Stone
出处
期刊:IEEE Transactions on Computers [Institute of Electrical and Electronics Engineers]
卷期号:C-19 (1): 73-78 被引量:220
标识
DOI:10.1109/tc.1970.5008902
摘要

If, as presently projected, the cost of microelectronic arrays in the future will tend to reflect the number of pins on the array rather than the number of gates, the logic-in-memory array is an extremely attractive computer component. Such an array is essentially a microelectronic memory with some combinational logic associated with each storage element. A logic-in-memory computer is described that is organized around a logic-enhanced ``cache'' memory array. Used as a cache, a logic-in-memory array performs as a high-speed buffer between a conventional CPU and a conventional memory. The effect on the computer system of the cache and its control mechanism is to make the main memory appear to have all of the processing capabilities and almost the same performance as the cache. Operations within the array are naturally organized as operations on blocks of data called ``sectors.'' Among the operations that can be performed are arithmetic and logical operations on pairs of elements from two sectors, and a variety of associative search operations on a single sector. For such operations, the main memory of the computer appears to the program to be composed of a collection of logic-in-memory arrays, each the size of a sector. Because of the high-speed, highly parallel sector operations, the logic-in-memory computer points to a new direction for achieving orders of magnitude increase in computer performance. Moreover, since the computer is specifically organized for large-scale integration, the increased performance might be obtained for a comparatively small dollar cost.

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