锁相环
PLL多位
带宽(计算)
控制理论(社会学)
dBc公司
相位噪声
电子工程
计算机科学
偏移量(计算机科学)
工程类
电信
人工智能
程序设计语言
控制(管理)
作者
Javad Tavakoli,Hossein Yaghobi,Samad Sheikhaei
标识
DOI:10.1109/icee52715.2021.9544135
摘要
A wide bandwidth integer-N Type-I PLL is proposed in this paper. By using a novel Delay-line based filter as loop filter, presented PLL achieves a loop bandwidth about 5 times greater than that of standard type-I PLL. The chosen strategy in widening the PLL bandwidth is to replace the RC loop filter with a 2-tap delay-line based filter which provides a desired magnitude and phase response. Presented PLL obtains a loop bandwith of about 5MHz with an input reference frequency of 10MHz, and also -50dBc spur level is achieved. - 119 dBc/Hz in-band phase noise at 1MHz offset is obtained from simulation. PLL total power consumption is 2.5mW from the nominal supply of 1.8V.
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