Successive Approximation Register TDC in Time-Mode Signal Processing

An 8-bit time-mode pseudo-differential successive approximation register time-to-digital converter (SAR TDC) is presented. The TDC achieves a high resolution and a better power/area efficiency using a pair of 16-stage pre-skewed delay line for 4-bit coarse digital-to-time conversion and a pair of digital time interpolators for 4-bit fine digital-to-time conversion. The architecture, operation, and design details of the TDC are provided. The pseudo-differential signaling of the TDC is examined and timing errors caused by device noise are studied. The TDC is designed in a TSMC 130 nm 1.2 V CMOS technology and analyzed using Spectre with BSIM3.3 device models. Simulation results show the TDC achieves 6.6 ps resolution, 7.1 ENOB, and 0.37 pJ/conversion FOM at 10 MS/s.