互连
可靠性(半导体)
材料科学
钝化
阻挡层
降级(电信)
电容
节点(物理)
光电子学
电子工程
氮化钽
缩放比例
图层(电子)
计算机科学
复合材料
电极
工程类
结构工程
化学
功率(物理)
物理
计算机网络
量子力学
物理化学
几何学
数学
作者
Shi You,Ren He,Mehul Naik,Lu Chen,Feng Chen,Carmen Leal Cervantes,Xiangjing Xie,Keyvan Kashefizadeh
标识
DOI:10.1109/iitc51362.2021.9537559
摘要
The continued scaling in logic technology poses significant challenges such as huge resistance-capacitance (RC) delays due to the shrinkage in dimensions. To address the BEOL Cu interconnect portion of RC delays, reducing the via resistance through Tantalum Nitride (TaN) barrier layer adjustment is critical while in the meantime must meet the reliability requirement. TaN barrier on via bottom contribute the major portion of Via R due to its high resistivity. Thinner TaN barrier approach, however, is limited due to its degraded barrier performance; In this paper, we presented the study of selective barrier approach that utilize gas phase metal passivation method to provide barrier free via bottom. >50% via R reduction is demonstrated with no reliability degradation.
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