Multi-Voltage GPIO Design and its Physical Implementation
计算机科学
嵌入式系统
计算机体系结构
作者
Rahul Shrivastava,Kishor Sarawadekar
出处
期刊:International Conference for Convergence for Technology日期:2018-10-01被引量:1
标识
DOI:10.1109/i2ct42659.2018.9058052
摘要
In this paper, we have shown the design andworking of a general purpose input output (GPIO) pin with multiple IO voltage levels. GPIO pin is a generic pin which can be used as input or output. This GPIO pin supports different voltage levels of IO devices. Its behaviour is controlled by the user by changing programmable control bit. Cadence Virtuoso design suite is used to design and simulate this GPIO pin. Next, layout is designed on Virtuoso layout editor. Layout is verified using Mentor Graphics Calibre tool. Post layout simulation is done on Synopsys Hspice tool. Thus, a full cycle of ASIC design has been implemented. This design uses 3.3 V transistors in 180 nm technology. The proposed GPIO pin can work up to 20MHz frequency.