Highly Stackable 3D Capacitor-Less DRAM for a High-Performance Hybrid Memory

This letter proposes a novel capacitor-less dynamic random-access memory composed of a 3D stacked cell array. To perform selective program and erase operations in the 3D cell array, a back-gate-sharing and channel-separating architecture are adopted. The operation of the unit cell is demonstrated through 3D technology computer-aided design simulations. The proposed device uses a simple process to optimize the back gate (e.g., modifying the thickness of materials or using different types of materials). Through optimization of the back gate, a sensing margin and retention time of 52 $\mu \text{A}$ and 475 ms, respectively, are achieved at 300 K in a scaled cell with a gate length of 30 nm and channel radius of 30 nm. Because this device has a cell array similar to that of a 3D NAND flash memory, it can be manufactured using the same process and equipment in a cost-effective manner. In addition, it can be adopted in processing-in-memory applications to provide high-performance and high-density hybrid memory functionality when used in conjunction with NAND flash memories.