Improved Parasitic Capacitance-Predictively Aware DTCO: Enhanced Cell Efficiency With Manufacturability and Scalability for 4F$^{\text{2}}$ VCT-Based DRAM

The 4F $^{{\text{2}}}$ cell architecture dynamic random access memory (DRAM) has emerged as a candidate for high-density future DRAM, meeting performance, power, area, and cost (PPAC) targets. This study proposes an improved parasitic capacitance-predictively aware design technology co-optimization (DTCO) flow that optimizes the bitline (BL) capacitance from structure and process perspectives, emphasizing manufacturability and scalability. A novel BL process flow is developed to optimize BL capacitance with scalability, utilizing a high-accuracy 3-D field solver for parasitic capacitance extraction of the vertical channel transistor (VCT) array. When air gap is used as the novel BL spacer, the BL capacitance decreases by 49.5%. In addition, we investigate and optimize the PPAC of the DRAM one transistor and one capacitor (1T1C) cell. The novel BL of 4F $^{{\text{2}}}$ VCT-based 1T1C DRAM demonstrates a 66.6% reduction in BL dynamic power consumption during read/write operations, with 9.4% and 11.6% enhancement in read speed when reading data "1" and "0", respectively. Moreover, a 58.8% reduction in cell array area and lower costs is yielded compared with the current VCT.