变压器
电气工程
正激变换器
反激变换器
电压
电子工程
计算机科学
升压变换器
工程类
作者
Obulapathi Balapanuru,Makarand M. Lokhande,Mohan V. Aware
摘要
Abstract The standard structure of an isolated SEPIC (iSEPIC) does not have a minimum‐phase nature, which signifies no additional support for the output capacitor during ON‐time conditions. Consequently, it has high voltage stress, right half plane (RHP) zeros presence, DC component in the transformer core, and less transformer utilization. This paper presents a modification in a iSEPIC converter having higher voltage gain over a conventional iSEPIC converter. This work analyzes a modified iSEPIC structure by providing additional support to the output capacitor during ON‐time conditions. As a result, the nonminimum‐phase nature will be transformed into the minimum‐phase nature. Consequently, all the mentioned demerits of the standard iSEPIC structure are eliminated The derived discrete‐time modeling analyzes the RHP zeros dependence on the load variation. This modification also leads to improvement in dynamic performance to accommodate the load variation. Finally, a 60 W modified iSEPIC prototype is developed to validate the proposed analysis.
科研通智能强力驱动
Strongly Powered by AbleSci AI