电流(流体)
材料科学
光电子学
双层
国家(计算机科学)
工程物理
纳米技术
电气工程
计算机科学
物理
化学
工程类
膜
生物化学
算法
作者
Xueping Li,Xiaojie Tang,Zhuojun Wang,Peize Yuan,Lin Li,Chenhai Shen,Congxin Xia
标识
DOI:10.1007/s11467-023-1390-3
摘要
Dielectric engineering plays a crucial role in the process of device miniaturization. Herein we investigate the electrical properties of bilayer GaSe metal-oxide-semiconductor field-effect transistors (MOSFETs), considering hetero-gate-dielectric construction, dielectric materials and GaSe stacking pattern. The results show that device performance strongly depends on the dielectric constants and locations of insulators. When high-k dielectric is placed close to the drain, it behaves with a larger on-state current (Ion) of 5052 µA/µm when the channel is 5 nm. Additionally, when the channel is 5 nm and insulator is HfO2, the largest Ion is 5134 µA/µm for devices with AC stacking GaSe channel. In particular, when the gate length is 2 nm, it still meets the HP requirements of ITRS 2028 for the device with AA stacking when high-k dielectric is used. Hence, the work provides guidance to regulate the performance of the two-dimensional nanodevices by dielectric engineering.
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