材料科学
阳极连接
晶片键合
氧化物
芯片级封装
小型化
抛光
热压连接
薄脆饼
引线键合
等离子体活化
复合材料
光电子学
炸薯条
纳米技术
图层(电子)
等离子体
计算机科学
冶金
物理
电信
量子力学
作者
Bohee Hwang,Sanwi Kim,Jeong‐Hwan Lee,Soo-Hwan Lee,Youngkun Jee,Sangcheon Park,Gyeongjae Jo,Kwangbae Kim,Sungjin Han,Il-Hwan Kim,Jumyong Park,Hyunchul Jung,Dongwoo Kang,Un-Byoung Kang
标识
DOI:10.1109/ectc51909.2023.00022
摘要
Hybrid copper bonding technology (HCB) has been developed to reduce the joint gap of stacked chips to the limit for miniaturization of I/O pitch and high heat dissipation. Especially, a critical parameter for multi stack applications is to enhance the bonding strength of oxide interfaces in die-to-wafer (D2W) bonding integration by the surface activation process including plasma treatment, hydration and cleaning before a chip to chip bonding step. Applying the established bonding technology, chemical mechanical polishing (CMP), and the optimized plasma surface activation process, we successfully demonstrated 3D DRAM packages up to 16 stacks. Despite the current development of surface activation sequences, detailed mechanisms of improved bonding strength related to plasma condition have yet been evaluated at the chip level. In this study, we discuss the effect of different plasma treatments on the bonding strength between the oxide interfaces. In particular, a methodology to evaluate oxide interface is proposed. To analyze the quality of the bonding interface of 16 stacked chips in HCB, it is crucial to measure the bonding strength for the bonded thin dies, which have a limitation to evaluate by utilizing conventional die shear test. We have established a novel method of measuring die level bonded interface by applying modified single-beam cantilever (SBC) method with stacked thin dies. By the optimum surface activation and bonding process through the developed analysis method, we have achieved 16 stacked D2W package.
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