校准
常量(计算机编程)
电阻抗
计算机科学
电气工程
数学
工程类
统计
程序设计语言
作者
Wenli Xu,Bingbing Yao,Qide Cheng,Zihao Du,Lei Qiu
出处
期刊:IEEE Transactions on Circuits and Systems Ii-express Briefs
[Institute of Electrical and Electronics Engineers]
日期:2024-01-01
卷期号:: 1-1
标识
DOI:10.1109/tcsii.2024.3401448
摘要
This paper proposes a signal-independent background calibration technique to compensate for offset, gain and timing skew mismatches in time-interleaved analog-to-digital converters (TIADCs). In this topology, a crude user-provided calibration signal is applied and alternatively sampled by all the interleaved channels. Based on the digitized codes of the calibration signal, which is independent of the input signal, multiple estimation algorithms could be used to extract these mismatches. To avoid interrupting the normal signal conversion operation, an extra sub-ADC channel is employed to cycle through and substitute for the interleaved channels to sample the analog input. The FPGA-based hardware implementation results show that the proposed calibration architecture combined with a statistics-based timing skew estimation method, successfully compensates the timing skew mismatch, with an input of DC voltage, single tone near Nyquist and random signal, respectively. Compared with traditional reference-ADC-based calibration schemes, except for the signal-independent characteristic, the proposed scheme avoids time-variant input impedance problem and achieves constant convergence time regardless of the inputs.
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