Double Pulse Test of the Paralleled Power MOSFETs in High Current 48V Inverter Design

Paralleling the discrete power MOSFETs is essential in low voltage (LV) high current inverter designs as such as 48V inverters in the automotive applications. In this paper, the effect of the main stray inductances and circuit mismatches are investigated. The effects of these placement variants and parasitics can be seen on drain-source voltage (V DS ) and drain current (I D ) waveforms during transient conditions. Therefore, Double Pulse Test (DPT) is a very efficient method to monitor unexpected switching behavior and unequal current distribution. The results from different placement configurations while using paralleled MOSFETs in the LV inverter designs are covered by this study and the results from the simulation, analytical calculations, and testbench are considered. Analytical calculations, simulation results, and the laboratory measurements are presented as an illustration of the proposed approach.