分频器
占空比
师(数学)
功率(物理)
CMOS芯片
分流器
倍频器
电子工程
电气工程
工程类
计算机科学
电压
物理
数学
量子力学
算术
作者
Ravi Kumar,Rajasekhar Nagulapalli,Rushikesh Hake,Santosh Kumar Vishvakarma
标识
DOI:10.1109/icecet55527.2022.9873078
摘要
This paper presents a novel optimized low-power multi-modulus programmable frequency divider with a modulus range of 2-to-7 with 50% output duty cycle for high-speed applications. The proposed divider is demonstrated with the division range from 2-127, which can be extended by adding more stages of the 2/3 Prescaler in the divider chain. The whole design is implemented using $0.18- \mu \mathrm{m}$ CMOS process with a supply of 1.8 V. From simulations result, the proposed design achieves a maximum operating frequency of 5 GHz with 6.5 mW of power consumption in divide-by-127 mode of operation while providing the 50% output duty cycle.
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