4-Layer Wafer on Wafer Stacking Demonstration with Face to Face/Face to Back Stacked Flexibility Using Hybrid Bond/TSV-Middle for Various 3D Integration

Different from Chip on Wafer stacking technology, Wafer on Wafer (WoW) stacking can provide a tighter pitch and higher interconnect density with higher through-put. The difficulty for WoW stacking is on wafer surface and edge treatment. In this work, a 4-layer WoW stacking architecture on 12 -inch wafers with hybrid bonding/bump-less and through-silicon-via (TSV) middle techniques for enabling various 3D integration has been demonstrated and proposed. It projects $\gt 15 \%$ form factor and $\gt 10 \%$ interconnection resistance reduction than typical scheme. Low process temperature $\left(180^{\circ} \mathrm{C}-250^{\circ} \mathrm{C}\right)$ is implemented for whole stacking process. Depending on different applications, both of wafers by Face to Face (F2F) and Face to Back (F2B) stacking processes are developed. For bump-less HBM-like structure, it needs special temporary bond and de-pond process for F2B bonding. F2F bonding can present a high dense interconnection for logic to memory AI computing application. The results of 4 layers (TSV $x 3$ and hybrid bond interface $x 3$) show that interconnection resistance is $\lt 0.25 \Omega$ per loop. It contains 17Kea of TSVs $\left(5 \mathrm{E} 3 / \mathrm{mm}^{2}\right)$ and 230Kea of hybrid bond pads $\left(2 \mathrm{E} 5 / \mathrm{mm}^{2}\right)$. From the eye-diagram and insertion loss simulation, hybrid bond/bump-less scheme leads to $\sim 40 \%$ performance improvement than it in the bump scheme.