Large-Area, Ultrathin Metal-Oxide Semiconductor Nanoribbon Arrays Fabricated by Chemical Lift-Off Lithography

材料科学 平版印刷术 Lift(数据挖掘) 光电子学 纳米技术 半导体 氧化物 金属 冶金 计算机科学 数据挖掘
作者
Chuanzhen Zhao,Xiaobin Xu,Sang‐Hoon Bae,Qing Yang,Wenfei Liu,Jason N. Belling,Kevin M. Cheung,You Seung Rim,Yang Yang,Anne M. Andrews,Paul S. Weiss
出处
期刊:Nano Letters [American Chemical Society]
卷期号:18 (9): 5590-5595 被引量:29
标识
DOI:10.1021/acs.nanolett.8b02054
摘要

Nanoribbon- and nanowire-based field-effect transistors (FETs) have attracted significant attention due to their high surface-to-volume ratios, which make them effective as chemical and biological sensors. However, the conventional nanofabrication of these devices is challenging and costly, posing a major barrier to widespread use. We report a high-throughput approach for producing arrays of ultrathin (∼3 nm) In2O3 nanoribbon FETs at the wafer scale. Uniform films of semiconducting In2O3 were prepared on Si/SiO2 surfaces via a sol–gel process prior to depositing Au/Ti metal layers. Commercially available high-definition digital versatile discs were employed as low-cost, large-area templates to prepare polymeric stamps for chemical lift-off lithography, which selectively removed molecules from self-assembled monolayers functionalizing the outermost Au surfaces. Nanoscale chemical patterns, consisting of one-dimensional lines (200 nm wide and 400 nm pitch) extending over centimeter length scales, were etched into the metal layers using the remaining monolayer regions as resists. Subsequent etch processes transferred the patterns into the underlying In2O3 films before the removal of the protective organic and metal coatings, revealing large-area nanoribbon arrays. We employed nanoribbons in semiconducting FET channels, achieving current on-to-off ratios over 107 and carrier mobilities up to 13.7 cm2 V–1 s–1. Nanofabricated structures, such as In2O3 nanoribbons and others, will be useful in nanoelectronics and biosensors. The technique demonstrated here will enable these applications and expand low-cost, large-area patterning strategies to enable a variety of materials and design geometries in nanoelectronics.
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