与非门
可靠性(半导体)
堆积
计算机科学
钥匙(锁)
缩放比例
块(置换群论)
材料科学
电子工程
频道(广播)
工程类
计算机网络
化学
操作系统
物理
功率(物理)
量子力学
数学
有机化学
几何学
标识
DOI:10.1109/edtm47692.2020.9117872
摘要
As scaling of 2D-NAND reached severe limitations several years ago, the industry has transitioned to 3D-NAND array architectures that are enabling continued scaling through stacking of cells in the vertical dimension. While 3D-NAND cells have inherent capability advantages due to the larger cell size and gate all-around structure, there are also several unique and particularly severe reliability mechanisms at play. Here, we will briefly review the physical model understanding of some of the key mechanisms impacting reliability on 3D-NAND, arising from the polysilicon channel with its grain boundaries, floating body, new block architecture, silicon nitride charge-trap layer, and virtual source/drain.
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