Single mask solution to pattern BLP and SNLP using 0.33NA EUV for next-generation DRAM manufacturing

As the industry continues to scale DRAM cell size, EUV lithography techniques have been considered in one or multiple steps. We have explored a single mask solution to pattern the bit-line-periphery (BLP) and the storage node landing pad (SNLP). Normally, for such varied types of structures as honeycomb arrays, SWD, S/A and Core, multiple masks are required. In this paper, we have explored a single EUV mask approach. First, a freeform EUV light source (in the source mask optimization, or SMO, process) was generated targeting a 36nm pitch honeycomb array and BLP structures. Then, curvilinear optical proximity correction (OPC) was applied to the target design (as shown in Figure 1) such that the performance meets qualified process window variation bands (PVBs) with proper curvilinear mask rule check (MRC). It is important to note that only an optical model was used for SMO and OPC without a resist model in this task. For the wafer process, we have used a dark field mask and metal oxide resist (MOR) photoresist and negative tone development (NTD). This was followed by transferring the pattern into a suitable hardmask for optical defect characterization using the KLA broadband plasma (BBP) 29xx tool as shown in Figure 2. Process window characterization was done to discover a unified defect-free window for both honeycomb array and BLP structures.