总谐波失真
线性
放大器
计算机科学
电子工程
数学
电气工程
拓扑(电路)
CMOS芯片
工程类
电压
作者
Huajun Zhang,Marco Berkhout,Kofi A. A. Makinwa,Qinwen Fan
出处
期刊:IEEE Journal of Solid-state Circuits
[Institute of Electrical and Electronics Engineers]
日期:2023-12-01
卷期号:58 (12): 3470-3480
标识
DOI:10.1109/jssc.2023.3318731
摘要
This article presents a digital-input class-D amplifier (CDA) achieving high dynamic range (DR) by employing a chopped capacitive feedback network and a capacitive digital-to-analog converter (DAC). Compared with conventional resistive-feedback CDAs driven by resistive or current-steering DACs, the proposed architecture eliminates the noise from the DAC and feedback resistors. Intermodulation between the chopping, pulsewidth modulation (PWM), and DAC sampling frequency is analyzed to avoid negative impacts on the DR and linearity. Real-time dynamic element matching (RTDEM) is employed to address distortion due to mismatch in the DAC, while its intersymbol interference (ISI) is eliminated by deadbanding. The prototype, implemented in a 180-nm bipolar, CMOS, and DMOS (BCD) process, achieves 120.9 dB of DR and a peak total harmonic distortion plus noise (THD $+$ N) of $-$ 111.2 dB. It can drive a maximum of 15/26 W into an 8-/4- $\Omega$ load with a peak efficiency of 90%/86%.
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