电压
电容器
可扩展性
拓扑(电路)
电气工程
带宽(计算)
电子工程
CMOS芯片
开关电容器
系统总线
计算机科学
数据转换
工程类
计算机硬件
电信
数据库
作者
Alessandro Dago,Mattia Balutto,Stefano Saggini,Mauro Leoncini,Salvatore Levantino,Massimo Ghioni
标识
DOI:10.1109/apec48139.2024.10509193
摘要
This paper introduces a novel scalable hybrid resonant converter based on the Dickson switched capacitor converter (SCC) structure for 48 V bus down-conversion. The conversion of the 48 V bus to the CPU/GPU core voltage typically includes a two-step process. First, an unregulated intermediate bus converter generates an intermediate bus voltage, commonly around 12 V. Then, a high-bandwidth multiphase voltage regulation module (VRM) provides the regulated core voltage. A lower intermediate bus voltage offers several advantages such as relaxed VRM specifications or the on-chip implementation of integrated and fully integrated voltage regulators (IVR/FIVR) in CMOS technology. To achieve a lower intermediate bus voltage, the proposed hybrid resonant SCC utilizes a multi-tapped autotrans-former (MTA) for increasing the conversion ratio. A prototype designed for converting 48 V to 3.4 V has been implemented to validate the proposed topology. A peak efficiency of 96.6 % and a maximum output current of 260 A are demonstrated. With a 48 V input voltage, the converter achieves a maximum power density of 920 W/inch 3 .
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