微电子
原子层沉积
CMOS芯片
纳米技术
材料科学
电介质
工程物理
电气工程
图层(电子)
光电子学
工程类
作者
Xiaolin Shi,C. Li,Hong Ji,Hao Qin,W. Zhang,Weizhi Xia,P.W. Ding
标识
DOI:10.1109/cstic.2018.8369251
摘要
Atomic Layer Deposition (ALD) is being used for many applications in advanced CMOS technologies, e.g. hi-k materials as gate dielectric, metal materials as metal gate electrode, dielectric spacers for self-aligned double patterning (SADP) or quadruple patterning (SAQP), and metal materials as Cu diffusion barrier layer etc. Beijing NAURA Microelectronics is the largest Chinese semiconductor equipment vendor. Its products cover many IC manufacturing fields, e.g. Etch, PVD, CVD, Furnace, and Cleaning etc. With the growing Chinese semiconductor market, NAURA expends its business into ALD field and develops ALD tools and processes to meet its customers' requirements. In this paper, we are going to review the ALD applications in advanced CMOS technologies, and discuss the ALD solutions which NAURA is capable to offer in advanced CMOS technologies.
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