Improved device characteristics obtained in 4H-SiC MOSFET using high-k dielectric stack with ultrathin SiO2-AlN as interfacial layers

A novel method of stacking dielectric layers on top of Silicon carbide (SiC) is proposed to address the most common Silicon dioxide (SiO2)-SiC interface issues in SiC based metal oxide semiconductor (MOS) devices. Aluminum nitride (AlN) as an interfacial layer, instead of SiO2, between hafnium oxide (HfO2) and SiC showed improved device characteristics. However, incorporating SiO2 along with AlN as an interfacial layer is found to be the best way of stacking dielectric layers. This is concluded, based on the changes observed in the electrical characteristics of the device by intentionally varying lattice temperature (T), interface trap density (Dit) and junction field effect transistor (JFET) width. All the investigations are done in 4H-SiC half-cell planar n-channel MOS field effect transistor (MOSFET) using commercially available technology computer aided design (TCAD) software sentaurus device. Theoretical calculations show good agreement with the simulated results, and are compared with the published results.