A 25.6-27.5GHz Phase-Locked Loop for SerDes Transceiver Clocking in 5nm FinFET

This paper presents a 25.6-27.5GHz integer-N Phase-Locked Loop (PLL) implemented in a 5nm FinFET process technology. The PLL incorporates a class-B LC VCO, a low-ripple PFD+CP and a wide-range programmable feedback divider. Targeting at 26.56GHz for a 106Gb/s Serializer-Deserializer (SerDes) application, the test chip achieves <90fs-rms jitter (integrated from 100Hz to Nyquist frequency) and <-120dBc reference spur with a CDR highpass bandwidth of 4MHz, for a power consumption of ~28mW from 0.875V supply.