Research on Interface Properties of Thermally Grown SiO2 and ALD SiO2 Stacked Structures

This study presents a stacked process of thermal and atomic layer deposition (ALD) SiO 2 that reduces the interface trap density of 4H-SiC metal-oxide-semiconductor (MOS) capacitors. The channel mobility of metal-oxide-semiconductor field effect transistors (MOSFETS) are reduced due to the high interface trap density as well as coulomb scattering mechanism. Herein, we investigate SiO 2 /SiC interface properties of a stacked process, which is accomplished via reducing the thickness of thermal oxidation film. Notably, MOS capacitors fabricated with thermal and ALD SiO 2 stacked structures can reduce the interface states density (D it ) by twofold at 0.2 eV below the conduction band energy compared with thermally grown SiO 2 . Additionally, the leakage current increases at a relatively slow rate in the electric field of 5–10 MV cm −1 , whereas the leakage current increases sharply when the electric field is higher than 10 MV cm −1 . The resultant ALD SiO 2 stacked structure provides a new approach to improving interface quality, which allows a reduction in the thermal budget involved in the fabrication of devices.