Resolving Issues of VTH and ILeak for P-Type LTPS TFT-Based Emission Gate Driver by Reducing Falling Time and Increasing Stabilizing Period for Smartwatch Displays

This work proposes an emission (EM) gate driver that is based on p-type low-temperature poly-crystalline silicon thin-film transistors (LTPS TFTs) with the implementation of lightly doped drain (LDD) to achieve flat off current. The long-tail phenomenon associated with the EM signal that is caused by a high threshold voltage (VTH) and (VTH variation in LTPS TFTs is improved by enhancing the driving capability of the pull-down TFT. The pulse width of the EM signal is adjustable, and the gate driver has a stabilizing structure to reduce the voltage deviation caused by the high leakage current ( $\text{I}_{\text {Leak}}{)}$ of LTPS TFTs; it keeps the EM signal at its lowest voltage level for 96.7% of the duration of a frame. Measurements indicate that the proposed structure shortens the falling time of the EM signal to $3.815 ~\mu \text{s}$ , which is much shorter than a horizontal time of $46 ~\mu \text{s}$ , yielding an EM signal with low distortion. An accelerated lifetime test demonstrates the high reliability of the proposed gate driver, which has the potential for driving active-matrix organic light-emitting diodes (AMOLEDs) smartwatch displays.