单层
接触电阻
范德瓦尔斯力
电流(流体)
材料科学
晶体管
场效应晶体管
凝聚态物理
纳米技术
光电子学
化学
电气工程
物理
图层(电子)
工程类
电压
分子
有机化学
作者
Miaomiao Li,Xinyu Zhang,Zimei Zhang,Gang Peng,Zhihong Zhu,Jia Li,Shiqiao Qin,Mengjian Zhu
出处
期刊:Nano Research
[Springer Nature]
日期:2024-08-27
卷期号:17 (11): 10162-10169
被引量:11
标识
DOI:10.1007/s12274-024-6942-5
摘要
High-performance field-effect transistors (FETs) based on atomically thin two-dimensional (2D) semiconductors have demonstrated great promise in post-Moore integrated circuits. However, unipolar p-type 2D semiconductor transistors yet remain challenging and suffer from low saturation current density (less than 10 µA·µm−1) and high contact resistance (larger than 100 kΩ·µm), mainly limited by the Schottky barrier induced by the mismatch of the work-functions and the Fermi level pinning at the metal contact interfaces. Here, we overcome these two obstacles through van der Waals (vdW) integration of high work-function metal palladium (Pd) as the contacts onto monolayer WSe2 grown by chemical vapor deposition (CVD) method. We demonstrate unipolar p-type monolayer WSe2 FETs with superior device performance: room temperature on-state current density exceeding 100 µA·µm−1, contact resistance of 12 kΩ·µm, on/off ratio over 107, and field-effect hole mobility of ~ 103 cm2·V−1·s−1. Electrical transport measurements reveal that the Fermi level pinning effect is completely effectively eliminated in monolayer WSe2 with vdW Pd contacts, leading to a Schottky barrier-free Ohmic contact at the metal-semiconductor junctions. Combining the advantages of large-scale vdW contact strategy and CVD growth, our results pave the way for wafer-scale fabrication of complementary-metal-oxide-semiconductor (CMOS) logic circuits based on atomically thin 2D semiconductors.
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