CMOS芯片
电路设计
计算机科学
水准点(测量)
集成电路设计
物理设计
电气工程
过程集成
电子工程
三维集成电路
集成电路
平面的
电子线路
标准电池
数字电子学
晶体管
嵌入式系统
工程类
电压
计算机图形学(图像)
地理
大地测量学
工艺工程
作者
F. Andrieu,P. Batude,Laurent Brunet,C. Fenouillet-Béranger,Didier Lattard,Sébastien Thuries,O. Billoint,R. Fournel,M. Vinet
出处
期刊:International Conference on IC Design and Technology
日期:2018-06-01
卷期号:: 141-144
被引量:14
标识
DOI:10.1109/icicdt.2018.8399776
摘要
In this paper, we review the main opportunities brought by 3D-monolithic integration for CMOS device and digital circuit. Simulation results show that 3D monolithic integration can provide up to 30% power reduction at iso-performance and 30% manufacturing cost saving for digital circuits, compared to planar technology, making it an attractive alternative to the straightforward technology scaling. We benchmark the transistor-level and cell-level 3D-monolithic integrations, where the inter-tier vias (3D-contacts) are used intra-cell or inter-cell, respectively. On the one hand, transistor-level 3D-integration can be seen as a full-custom approach, both in terms of technology and circuit design. It promises more performance but at the expense of strong Design/Technology Co-Optimizations. On the other hand, the cell-level 3D-integration ensures a 50% area reduction and a re-use of the technology/design platform. The main technology challenge relative to this integration is the thermal budget constraint of the top-level process integration and the intermediate Back-End-Of-Line (iBEOL) stability. Finally, the total isolation of the top-level transistors integrated in 3D-monolithic raises new opportunities and offers new functionalities like for example an efficient dynamic back-biasing capability.
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