Study of Electrical Characteristics for Dual-Gate TFTs With Asymmetric Defect Distributions and Gate Work Functions

Combined effects of asymmetric defect distributions and asymmetric gate work functions (WFs) on the performances of self-aligned dual-gate poly-Si TFTs are investigated. Normally, small grains with plentiful grain boundaries (GBs) or other structural defects appear at different positions of the poly-Si film, which is dependent on the growth process of the film. Subgap states of acceptor-like tail, acceptor-like deep-level, donor-like tail, and donor-like deep-level states are used to emulate the defects. Two sets of density of states (DOS) are employed. We find that defects at different positions of the source-side and drain-side channels exhibit different influences on TFT performance and the influences are dependent on the WFs of the gates. TFTs with a higher gate WF can have a higher tolerance to the depth of the defect region. Besides the electrical characteristics, the combined effects of defects and gate WFs on current density distributions and electric field distributions in the channel regions are explored. The performance variations caused by the asymmetric defects along with asymmetric gate WFs can be explained.