Digital Integrated Circuit Design

This chapter introduces the classification, design methods, and main features of digital ICs. Circuit partitioning is a valuable method to reduce the complexity of VLSI design, in which hardware description language (HDL) is used to model the concurrent execution process of hardware circuits, including Verilog and VHDL. High-level synthesis (HLS) transforms the behavioral-level description into circuit structure descriptions under certain constraints. Following the logic synthesis that transforms the register transfer level (RTL) description into the gate-level structure description, various methods are used to implement and verify a digital IC design, such as formal verification, the mathematical method to analyze circuit behavior to find circuit functional error, timing analysis to ensure the normal operation of the circuit including setup and hold time constraints, floor planning to place the main modules of the design to meet requirements for die size, as well as timing closure and routing. In addition, design for testability (DFT) is used to detect chip manufacturing defects by inserting extra units without changing the circuit function, and the hardware emulation uses dedicated hardware to perform circuit functions for the circuit function verification, etc.