期刊:IEEE Solid-State Circuits Magazine [Institute of Electrical and Electronics Engineers] 日期:2016-01-01卷期号:8 (4): 10-13被引量:27
标识
DOI:10.1109/mssc.2016.2603228
摘要
Since its introduction in the 1980s, true single-phase clock (TSPC) logic [1] has found widespread use in digital design. Originally proposed as a high-speed topology, the TSPC structure also consumes less power and occupies less area than other methods. In this article, we study the properties of this logic family.