静电放电
调试
计算机科学
物理设计
中间层
设计流量
集成电路
点(几何)
功能验证
互连
电子工程
电子线路
嵌入式系统
电气工程
工程类
电路设计
电压
形式验证
图层(电子)
程序设计语言
几何学
化学
有机化学
操作系统
蚀刻(微加工)
数学
计算机网络
算法
作者
Dina Medhat,Mohamed Dessouky,DiaaEldin Khalil
标识
DOI:10.1109/isqed48828.2020.9137046
摘要
Technology evolution from conventional 2D to 3D integrated circuits (ICs) has faced many challenges, among them electrostatic discharge (ESD) protection device design and verification. Several studies have addressed ESD device design for 3D ICs. However, once such designs are implemented, there is a lack of automated ESD physical verification methodologies. In this paper, we propose an automated ESD layout verification solution that addresses complete 2.5D/3D IC designs. The proposed flow covers protection schemes for both external and internal input/output interfaces. Moreover, it addresses total point-to-point parasitic resistance and current density analysis for relevant ESD interconnect routes across all dies and interposer to ensure they can handle any ESD event. An ESD verification testcase demonstrates the inputs setup for the flow, and shares results for different ESD violations to prove the effectiveness of the proposed solution for both detection as well as debugging.
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