A Framework for Evaluation of Debug Path Performance in SoC

With rapidly growing demands of debugging in embedded systems, the architecture of debug subsystem is becoming a challenging task to system designers. A typical multi-processor system-on-chip (MP-SoC) has several heterogeneous cores, and few other critical IPs whose tracing is important from debugging point of view. Typically, in on-the-fly host debugging mode, the minimum expectation is that the debug data path is able to provide sufficiently large instruction traces of all heterogeneous cores without any loss in non-invasive debug mode. For debug and diagnosis, a comprehensive run-time observation into the MPSoC shows how the software (e.g real-time) is executed. It becomes a challenging task in the pre-silicon stage to evaluate this performance requirement of debugging datapath in absence of an appropriate benchmark suite or appropriate bus functional model. Even, it is equally problematic to convince the customers after the post-silicon stage, about the competitive advantage of the device in terms of debugging. In this paper, we are proposing a performance evaluation framework for debug infrastructure of embedded devices (e.g ARM CoreSight) using few standard benchmarks and also, proposing a few performance metrics. It reduces the performance evaluation time and improved design quality significantly.