Highly Linear Ka-Band CMOS Linear Power Amplifier Using T-Shape Linearizer With pMOS

We present a broadband, highly linear, high gain efficient, Class-AB power amplifier (PA) using a T-shape linearizer with pMOS varactor (TSLP) process for fifth generation (5G) applications, which is verified using 65-nm bulk complementary metal-oxide-semiconductor (CMOS) process. The proposed linearization technique enhances the linearity by compensating the input capacitance non-linearity and terminates the second harmonic components simultaneously. As a result, it helps to operate the PA at its optimal operating point for higher efficiency without compromising linearity. The fully integrated three-stage differential PA shows a power gain of 33.0/32.1/31.8 dB, saturation output power ( $P_{\mathrm {OUT}}$ ) of 20.9/21.5/20.4 dBm, and peak power added efficiency (PAE) of 34.3%/40.0%/38.2% at 24/26/28 GHz. Without digital pre-distortion (DPD) or adaptive power tracking (APT), the proposed PA achieves a linear $P_{\mathrm {OUT}}$ of 14.8/15.3/14.2 dBm and an average PAE of 17.0%/20.4%/17.1% at 24/26/28 GHz for 100 MHz 5G new ratio (5G NR) OFDM signal at the EVM of −25 dB (peak to average power ratio (PAPR) of $>$ 10.0 dB and drain efficiency at main-stage only $>$ 21.1%/25.6%/21.7%). The three-stage PA is implemented with a core size of $0.241\,\,\mathrm {\times }\,\,0.96\,\,{\mathrm {mm}}^{2}$ .