Performance Evaluation of Parallel Tasks for Fault-tolerant Routing Methods

To realize high speed processing of parallel applications in high-end IoT devices, multi or many core processors are implemented on a VLSI chip. As the interconnection system of many core processors (nodes), Network-on-Chip (NoC) is attracted attention. In NoC, fault-tolerant routing plays an important role in communication between nodes. Many fault-tolerant routing methods have been studied and evaluated mainly in terms of communication performance. However, the evaluation of only communication performance is not sufficient; it is also necessary to evaluate execution time of parallel applications. We evaluated execution time of parallel applications for four fault-tolerant routing methods. We used parallel tasks generated by TGFF, and employed a genetic algorithm to obtain semi-optimal task mapping. Simulation result shows that the fault-tolerant routing method called Passage reduced application execution time by about 11%, compared with the method called Fcube4.