Design of an Efficient Parallel Random Number Generator Using a Single LFSR for Stochastic Computing

This paper proposes a parallel random number generator (RNG) using a single linear feedback shift register (LFSR) to generate two distinct random numbers, achieving twice the operational speed of a traditional serial RNG. The proposed RNG generates two distinct random numbers utilizing an LFSR. When implemented in a 65-nm CMOS technology, the proposed design leads to a 15.6% improvement in area and a 14.8 % improvement in power efficiency, addressing the trade-off between accuracy and energy efficiency in stochastic computing (SC). Furthermore, the proposed design not only matches but surpasses the performance of serial SC in an edge-detection digital image processing application. Therefore, for enhanced hardware efficiency and improved accuracy, the proposed parallel RNG architecture can be effectively employed.