Semidamascene Interconnects for 2nm node and Beyond

In this paper we present a semidamascene integration approach for interconnect devices as an alternative to dual damascene. A Ru layer is deposited to fill vias and provide an overburden in which we will form lines using subtractive metal etching, enabling easy access to higher line aspect ratios without the need for metal CMP. Subsequent dielectric deposition forms airgaps between the lines. Devices fabricated in imec’s 300mm cleanroom have demonstrated with >80% reproducibility for line structures with 30nm metal pitch. We also present reliability results with extrapolated lifetime > 10 years and benchmark the mechanical strength of semidamascene devices to traditional dual damascene.